This invention relates to electronic inverters and, more particularly, to controlling the operation of solid state switching devices in an output stage of such inverters.
Electronic inverters create an AC output voltage by alternately switching output terminals between one of two DC voltage levels. Total harmonic distortion in the output voltage can be minimized by precisely controlling the operation of the output circuit switching devices. Since the operating times of various switching devices depend upon individual device characteristics and changes in the load being supplied by the inverter, a switch drive circuit which adapts to changes in individual switch operating time is desired.
Inverters utilizing pulse width modulation or harmonic neutralization techniques require very accurate timing for control of the total harmonic distortion. Techniques for timing correction have been developed as illustrated in U.S. Pat. Nos. 4,443,842; 4,502,105; and, 4,504,899, for three-phase DC link inverters. Those circuits utilize a multiplexed correction control circuit compatible with a read only memory based switching pattern timing circuit. Such circuits are more complex than necessary for staggered phase or square wave, single phase inverters. It is therefore desirable to devise a timing correction circuit which is compatible with staggered phase or square wave, single phase inverters.